Performance Evaluation of Large Reconfigurable Interconnects for Multiprocessor Systems

Communication has always been a limiting factor in making efficient computing architectures with large processor counts. Reconfigurable interconnects can help in this respect, since they can adapt the interprocessor network to the changing communication requirements imposed by the running application. In this paper, we present a performance evaluation of these reconfigurable interconnection networks in the context of shared-memory multiprocessor (SMP) machines. We look at the effects of architectural parameters such as reconfiguration speed and topological constraints, and analyze how these results scale up with higher processor counts. We find that for 16 processors connected in a torus topology, reconfigurable interconnects with switching speeds in the order of milliseconds can provide up to 20% reduction in communication delay. For larger networks, up to 64 processors, the expected gain can rise up to 40%. This shows that reconfigurable networks can help in removing the communication bottleneck from future interconnection designs.